1. Field of the Invention
The invention concerns integrated circuits.
The problem to be solved is that of protecting the circuit against electrostatic discharges which may destroy certain elements of the circuit.
These electrostatic discharges may result quite simply from the component's being handled by an operator whose hands are not connected to a fixed potential, to the ground for example. The discharges occur between the input/output terminals of the component. They are passed on into the integrated circuit through the metallized pads deposited on the substrate in which the circuit is formed. These pads are connected to the external input/output terminals, generally by soldered conductive wires.
To make the integrated circuits immune to the destructive effects of these discharges, specific circuit elements are placed close to the metallized pads. These circuit elements are used chiefly to deflect the electrostatic discharge currents in order to prevent them from flowing within more fragile elements.
These protection elements should be capable of deflecting the greatest possible energy without being themselves destroyed and, despite this, they should take up as little space as possible. For, they are necessarily very bulky and use up a large part of the available integrated circuit surface. It is desired to achieve the utmost possible restriction of the space taken up by them, in order to reserve surface space for the integrated circuit proper.
2. Description of the Prior Art
FIG. 1 shows an example of a protection structure in the case of an integrated circuit made by NMOS technology on a P-type substrate. The protection structure comprises essentially an NPN type lateral bipolar transistor, with its collector connected to a pad to be protected and its emitter connected to another pad or to a reference potential. The base is formed by a portion of the substrate itself.
In FIG. 1, the P-type substrate is designated by the reference 10 and the pad to be protected has the reference 12. This pad is connected by a portion of metallisation 14 to an N+ type zone 16, superficially diffused in the substrate. This zone 16 forms the collector of the lateral NPN protection transistor. The zone 16 is separated laterally from another superficial N+ type diffused zone, designated by the reference 18, forming the emitter of the lateral NPN transistor. A base region 20, formed by the P-type substrate, separates the regions 16 and 18. This base region 20 is covered with a thick insulator layer 22 (silicon oxide). The emitter zone 18 is connected by a metal contact 24, for example to a reference potential which is preferably the low supply potential Vss of the circuit. The substrate is also connected to Vss.
FIG. 2 is a top view showing the relative arrangement of the pad to be protected, the diffused zones and the metallisations. The contour 120 is the contour of the metal pad 12, as it appears when the entire structure is protected by an insulating passivation layer not shown in FIG. 1. This layer covers the entire circuit except for the aperture defined by the contour 120. The contour 140 represents the metallization connected to the pad 12, including the pad 12. The contour 160 represents the N+ type diffused zone 18. The narrow space between these two contours represents the base 20 of the lateral transistor. The contour 240 represents the metallization 24 connected to Vss. The contour 165 represents the aperture of the insulating layer by which the metallization 14 can come into contact with the zone 16. Finally, the contour 185 represents the aperture of the insulator layer by which the metallization 24 can come into contact with the diffused zone 18.
When the pad to be protected receives electrostatic discharges having a positive bias with respect to the substrate, the lateral bipolar transistor will become conductive by the setting up of an avalanche in its base/collector junction, and then by direct conduction between the collector and the emitter.
During discharges with negative bias, the diode formed by the N+ type diffused zone 16 and the P-type substrate will be conductive in forward bias. Furthermore, the lateral bipolar transistor could be triggered to boost the conduction.
The limitation of the performance characteristics of this type of protection often arises out of the thermal destruction, from a certain level of energy onwards, of the edges of the contact between the metallization 14 connected to the pad 12 and the diffused zone 16. The heating due to the discharge current flowing through the protection transistor prompts a local migration of the metal of the contact (generally aluminum) which may go so far as to put the N+P junction, located just below, into short-circuit. The heating is at its maximum level on the edge of the contact, and it is at this place that there is destruction of the junction. This junction is only at a very small depth of 0.3 to 0.5 micrometer approximately.
FIG. 3 shows the short-circuit region 26 created by this heating.
The circuit is then unusable because the pad to be protected is placed permanently at the potential of the substrate by this permanent short-circuit.
In CMOS technology on a P substrate, the operation of diffusing N- wells is used to created a deep N- type zone just beneath the contact between the metallization 16 and the diffused N+ region. This has the effect of shifting the NP junction much further below, the depth of the N- well being rather in the region of 4 to 5 micrometers. Even if the edges of the contact get heated with a resultant localised fusion of the contact beneath these edges, the aluminum does not reach the depth of 4 to 5 micrometers and the NP insulator junction between the pad and the substrate remains intact.
FIG. 4 shows this arrangement. The references are the same as in the previous Figures. It shows the N-type localised well 28 beneath the contact. The zone of fusion 26 does not reach the trench/substrate junction. The pad is not short-circuited with the substrate.
Consequently, the CMOS substrates with P substrate and N well can bear electrostatic discharges with far higher energy levels than the NMOS circuits.
If this protection structure has to be transposed to the case of CMOS circuits on N-type substrate with P-type wells, the idea that comes naturally to mind is that of inverting all the types of conductivity to make a structure similar to that of FIG. 4 where all the P regions are replaced by N regions and vice versa. This entails the assumption that the lateral NPN transistor is replaced by a PNP lateral transistor. Experience shows that this type of structure does not work well, undoubtedly because of the slower reaction time of the PNP structure and its limited ability to conduct a high current.
The invention is aimed at proposing a protection structure for CMOS circuits on N substrate with P wells, that is more efficient than those of the prior art.